In recent years, with the adoption of microfabrication in semiconductor process technology, the rate of signal delay in relation to interconnections has increased. This has made it difficult to design timings to satisfy their specifications in design of semiconductor integrated circuits (LSI)
Conventionally, designers design and develop LSI circuits in the following manner. After a logic circuit design process with a logic synthesis tool and a layout design process with a layout tool, a designer performs timing analysis to examine whether or not an LSI circuit obtained through these processes satisfies the timings on the specifications. If the LSI circuit fails to satisfy the specifications, the designer determines that the layout design process should be repeated, or, in some instances, even determines that the design should be done again from the logic circuit design process.
FIG. 4 is a simplified illustration of the relation of timings in a part of LSI circuit design. Referring to FIG. 4, CC denotes a circuit portion to be analyzed, which includes a number of signal paths Path(i,j). Reg(i) and Reg(j) denote a start register and an end register, respectively, for the signal paths Path(i,j). Among propagation delays of a number of signal paths between the start register Reg(i) and the end register Reg(j), the minimum and maximum delay values are denoted by Wmin(i,j) and Wmax(i,j), respectively.
Suppose LSI design specifications include timing specifications satisfying a clock cycle T. In circuit design based on such specifications, if the maximum delay Wmax obtained after the circuit layout design fails to be shorter than the clock cycle T, it is impossible to complete data transfer through the signal path Path(i,j) within the clock cycle T. To avoid this trouble, conventionally, a delay analysis method as shown in FIG. 5 has been employed to analyze delays of signal paths. That is, a frequency distribution graph has been prepared for the maximum delays Wmax (i,j) of signal paths between all register pairs (i,j) of start and end registers, and generally used for delay analysis. This graph shows how the maximum delay Wmax is distributed and how an error is distributed with respect to the clock cycle T. As an example of such a system, Japanese Laid-Open Patent Publication No. 9-054138 discloses signal delay analysis by an interactive signal delay analysis method for semiconductor circuits, where the number of errors and the ratio thereof are presented in the form of a circle graph, and signal delay of a semiconductor circuit is analyzed based on the presented results.
Conventionally, designers have performed circuit design to satisfy targets on the design specifications using the frequency distribution graph. That is, when a majority of signal paths fail to satisfy the clock cycle T, the design method is reviewed starting from the logic circuit design process (major correction). When only a small number of signal paths fail to satisfy the clock cycle T, minute correction is made in the layout design process (minor correction).
The conventionally adopted frequency distribution graph or equivalent information thereof has the following problems. First, it fails to analyze the cause of a timing error generated by integration of a set-up error and clock delay. Secondly, it fails to analyze the cause of a timing error generated by integration of a hold error and clock delay. Thirdly, it fails to provide information essential for the current complicated design. For example, no design improvement indication is provided for a logic circuit section and a clock section.
An object of the present invention is facilitating analysis of the cause of a timing error generated by integration of a set-up error and clock delay and the cause of a timing error generated by integration of a hold error and clock delay, and also providing a design improvement indication for a logic circuit section and a clock section.
In facilitating the above analysis and providing a design improvement indication, if relevant information is output in the form of text files and the like, the information amount is enormous and thus it takes long time to perform timing analysis for satisfying the timing specifications. In view of this fact, another object of the present invention is providing a method for analyzing the cause of a timing error of an LSI circuit more intuitively and presenting the results suggesting measures to be taken, or an apparatus implementing the method.
In order to attain the above objects, according to the present invention, a general set-up condition or hold condition where clock delay is not 0 is presented on a two-dimensional graph.
The signal delay analysis method for a semiconductor circuit of the present invention includes the steps of: preparing a two-dimensional graph G defined by two axes of Si and Sj+Txe2x88x92Wmax or two axes of Sj and Sixe2x88x92T+Wmax where T is a clock cycle, Wmax is a maximum delay of a circuit portion to be analyzed, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion; and plotting delay analysis results of the circuit portion on the two-dimensional graph G prepared in the preparing step.
According to the present invention, in the signal delay analysis method for a semiconductor circuit described above, in the preparing step, an auxiliary line of Si=Sj+Txe2x88x92Wmax or an auxiliary line of Sj=Sixe2x88x92T+Wmax drawn diagonally from the origin may be added to the two-dimensional graph G prepared.
Alternatively, the signal delay analysis method for a semiconductor circuit of the present invention includes the steps of: preparing a two-dimensional graph G defined by two axes of Si and Sjxe2x88x92Wmin or two axes of Sj and Si+Wmin where Wmin is a minimum delay of a circuit portion to be analyzed, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion; and plotting delay analysis results of the circuit portion on the two-dimensional graph G prepared in the preparing step.
According to the present invention, in the signal delay analysis method for a semiconductor circuit described above, in the preparing step, an auxiliary line of Si=Sjxe2x88x92Wmin or an auxiliary line of Sj=Si+Wmin drawn diagonally from the origin may be added to the two-dimensional graph G prepared.
According to the present invention, in the signal delay analysis method for a semiconductor circuit, an indication of correcting the clock timing to the register may be displayed when the delay analysis results on the two-dimensional graph G expand in parallel with the axis Si or the axis Sj, and an indication of improving signal delay of the circuit portion may be displayed when the delay analysis results expand vertically to the axis Si or the axis Sj.
The design assist apparatus for a semiconductor circuit of the present invention includes: preparing means for preparing a two-dimensional graph G defined by two axes of Si and Sj+Txe2x88x92Wmax or two axes of Sj and Sixe2x88x92T+Wmax where T is a clock cycle, Wmax is a maximum delay of a circuit portion to be analyzed, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion; plotting means for plotting delay analysis results of the circuit portion on the two-dimensional graph G prepared in the preparing means; and indication means for displaying an indication of correcting the clock timing to the register when the delay analysis results on the two-dimensional graph G expand in parallel with the axis Si or the axis Sj, while displaying an indication of improving signal delay of the circuit portion when the delay analysis results expand vertically to the axis Si or the axis Sj.
Alternatively, the design assist apparatus for a semiconductor circuit of the present invention includes: preparing means for preparing a two-dimensional graph G defined by two axes of Si and Sjxe2x88x92Wmin or two axes of Sj and Si+Wmin where Wmin is a minimum delay of a circuit portion to be analyzed, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion; plotting means for plotting delay analysis results of the circuit portion on the two-dimensional graph G prepared in the preparing means; and indication means for displaying an indication of correcting the clock timing to the register when the delay analysis results on the two-dimensional graph G expand in parallel with the axis Si or the axis Sj, while displaying an indication of improving signal delay of the circuit portion when the delay analysis results expand vertically to the axis Si or the axis Sj.
Thus, according to the present invention, the necessary and sufficient conditional expression that should be satisfied to enable a semiconductor circuit to operate at a clock cycle T is presented in the form of a two-dimensional graph defined by two axes one of which is a clock timing. The delay analysis results of the circuit portion to be analyzed are plotted on the two-dimensional graph. This enables observation of how the clock timing varies. In addition, it is possible to easily determine whether the error is a set-up or hold error or a clock timing error.
Moreover, according to the present invention, the necessary and sufficient conditional expression is presented in the form of a two-dimensional graph defined by two axes one of which is a clock timing as described above. Therefore, when the delay analysis results are distributed vertically to the clock timing axis, it can be determined that the clock skew is small, and thus an indication of improving signal delay of the circuit portion can be provided. On the contrary, when the delay analysis results are distributed in parallel with the clock timing axis, it can be determined that the clock skew is large, and thus an indication of improving the clock circuit design can be provided.